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| FUJITSU SEMICONDUCTOR DATA SHEET AE1.0E MEMORY Mobile FCRAMTM CMOS 64M Bit (4 M word x 16 bit) Mobile Phone Application Specific Memory MB82DP04183C-65L CMOS 4,194,304-WORD x 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface DESCRIPTION The Fujitsu MB82DP04183C is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 67,108,864 storages accessible in a 16-bit format. This MB82DP04183C is suited for mobile applications such as Cellular Handset and PDA. FEATURES * Asynchronous SRAM Interface * Fast Access Time tCE = tAA = 65ns max * 8 words Page Access Capability tPAA = 20ns max * Low Voltage Operating Condition VDD = +2.6V to +3.1V * Wide Operating Temperature TA = -30C to +85C * Byte Control by LB and UB * Low Power Consumption IDDA1 = 40mA max IDDS1 = 90A max (@ +40C) * Various Power Down mode Sleep 8M-bit Partial 16M-bit Partial Notice: FCRAM is a trademark of Fujitsu Limited, Japan 1 (8/2004) MB82DP04183C -65L PRELIMINARY PIN DESCRIPTION Pin Name A21 to A0 CE1 CE2 WE OE UB LB DQ16-9 DQ8-1 VDD VSS Address Input Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Upper Byte Control (Low Active) Lower Byte Control (Low Active) Upper Byte Data Input/Output Lower Byte Data Input/Output Power Supply Ground Description BLOCK DIAGRAM VDD VSS A21 to A0 ADDRESS LATCH & BUFFER ROW DECODER MEMORY CELL ARRAY DQ16 to DQ9 DQ8 to DQ1 INPUT / OUTPUT BUFFER INPUT DATA LATCH & CONTROL SENSE / SWITCH COLUMN / DECODER ADDRESS LATCH & BUFFER OUTPUT DATA CONTROL CE2 POWER CONTROL TIMING CONTROL CE1 WE UB LB OE 2 (AE1.0E) MB82DP04183C -65L PRELIMINARY FUNCTION TRUTH TABLE Mode Standby (Deselect) Output Disable Output Disable (No Read) Read (Upper Byte) Note CE2 H *1 CE1 H WE X H OE X H UB X X H L LB X X H H L L H H L L X A21-0 X *3 Valid Valid Valid Valid Valid Valid Valid Valid X DQ16-9 High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid Invalid Input Valid High-Z DQ8-1 High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid Input Valid Input Valid High-Z H Read (Lower Byte) Read (Word) No Write Write (Upper Byte) L Write (Lower Byte) Write (Word) Power Down *2 L X X H L L H L H L H L X X *4 H Notes L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1: Should not be kept this logic condition longer than 1s. Please contact local FUJITSU representative for the relaxation of 1s limitation. *2: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Refer to POWER DOWN for the detail. *3: Can be either VIL or VIH but must be valid before Read or Write. *4: OE can be VIL during Write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. See Asynchronous Read / Write Timing #1-1 (CE1 Control) (2) OE stays VIL during Write cycle. 3 (AE1.0E) MB82DP04183C -65L PRELIMINARY POWER DOWN Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains low power idle state as long as CE2 is kept low. CE2 High resume the device from power down mode. This device has three power down mode, Sleep, 8M Partial and 16M Partial. The selection of power down mode can be programmed by series of read/write operation. Each mode has follwoing data retention features. Mode Sleep (default) 8M Partial 16M Partial Data Retention No 8M bit 16M bit Retention Address N/A 000000h to 07FFFFh 000000h to 0FFFFFh The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. Power Down Program Sequence The program requires total 6 read/write operation with unique address. Between each read/write operation requires that device be in standby mode. Following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 3FFFFFh (MSB) 3FFFFFh 3FFFFFh 3FFFFFh 3FFFFFh Address Key Data Read Data (RDa) RDa RDa Don't Care (X) X Read Data (RDb) The first cycle is to read from most significant address (MSB). The second and third cycle are to write to MSB. If the second or third cycle is written into the different address, the program is cancelled. And the data written at the second or third cycle is valid as a normal write operation. It is recommended to write back the data (RDa) read by first cycle to MSB in order to secure the data. The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth cycle is written into different address, the program is also cancelled but write data may not be written as normal write operation. The last cycle is to read from specific address key for mode selection. And read data (RDb) is invalid. Once this program sequence is performed from a Partial mode to the other Partial mode, the write data may be lost. So, it should perform this program sequence prior to regular read/write operation if Partial mode is used. Address Key The address key has following format. Address A21 1 1 1 A20 1 0 0 A19 1 1 0 A18 - A0 1 1 1 Binary 3FFFFFh 2FFFFFh 27FFFFh Mode Sleep (default) 8M Partial 16M Partial 4 (AE1.0E) MB82DP04183C -65L PRELIMINARY ABSOLUTE MAXIMUM RATINGS (See WARNING below.) Parameter Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature Symbol VDD VIN, VOUT IOUT TSTG Value -0.5 to +3.6 -0.5 to +3.6 +50 -55 to +125 Unit V V mA o C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS (See WARNING below.) (Referenced to VSS) Parameter Supply Voltage VSS High Level Input Voltage Low Level Input Voltage Ambient Temperature *1 *2 VIH VIL TA 0 VDD*0.8 -0.3 -30 0 VDD+0.2 VDD*0.2 85 V V V C Notes Symbol VDD Min. 2.6 Max. 3.1 Unit Notes *1: Maximum DC voltage on input and I/O pins are VDD+0.2V. During voltage transitions, inputs may positive overshoot to VDD+1.0V for periods of up to 5 ns. *2: Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot VSS to -1.0V for periods of up to 5ns. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 5 (AE1.0E) MB82DP04183C -65L PRELIMINARY DC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted)Note *1,*2,*3 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS VDD Power Down Current IDDP8 IDDP16 VDD = VDD max., VIN = VIH or VIL CE1 = CE2 = VIH VDD = VDD max., TA +85C VIN (including CLK) 0.2V or VIN (including CLK) VDD - 0.2V, TA +40C CE1 = CE2 VDD - 0.2V VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA, tPRC = min. tRC / tWC = minimum tRC / tWC = 1s VDD = VDD max., VIN = VIH or VIL, CE2 0.2V Test Conditions VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD(min), IOH = -0.5mA IOL = 1mA SLEEP 8M Partial 16M Partial Min. -1.0 -1.0 2.4 -- -- -- -- Max. +1.0 +1.0 -- 0.4 10 80 100 Unit A A V V A A A IDDS VDD Standby Current IDDS1 -- 1.5 mA A A mA mA -- -- 170 90 IDDA1 VDD Active Current IDDA2 -- -- 40 5 VDD Page Read Current IDDA3 -- 10 mA Notes *1: All voltages are referenced to Vss. *2: DC Characteristics are measured after following POWER-UP timing. *3: IOUT depends on the output load conditions. 6 (AE1.0E) MB82DP04183C -65L PRELIMINARY AC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) READ OPERATION Value Parameter Read Cycle Time CE1 Access Time OE Access Time Address Access Time LB / UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z LB / UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB / UB High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low Address Invalid Time Address Hold Time from CE1 High Address Hold Time from OE High WE High to OE Low Time for Read CE1 High Pulse Width Symbol Min. tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP 65 -- -- -- -- -- 20 5 5 10 0 -- -- -- -6 10 -- -6 -6 25 12 Max. 1000 65 40 65 30 20 1000 -- -- -- -- 20 14 20 -- -- 10 -- -- 1000 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *10 *5, *8 *9 *1, *2 *3 *3 *3, *5 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *3 *3 *3 Unit Notes Notes *1: Maximum value is applicable if CE1 is kept at Low without change of address input of A3 to A21. If needed by system operation, please contact local FUJITSU representative for the relaxation of 1s limitation. *2: Address should not be changed within minimum tRC. *3: The output load 50pF. *4: The output load 5pF. *5: Applicable to A3 to A21 when CE1 is kept at Low. *6: Applicable only to A0, A1 and A2 when CE1 is kept at Low for the page address access. *7: In case Page Read Cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4s. In other words, Page Read Cycle must be closed within 4s. *8: Applicable to address access when at least two of address inputs are switched from previous state. *9: tRC(min) and tPRC(min) must be satisfied. *10: If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. 7 (AE1.0E) MB82DP04183C -65L PRELIMINARY AC CHARACTERISTICS (Continued) WRITE OPERATION Value Parameter Write Cycle Time Address Setup Time CE1 Write Pulse Width WE Write Pulse Width LB / UB Write Pulse Width LB / UB Byte Mask Setup Time LB / UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width LB / UB High Pulse Width Data Setup Time Data Hold Time OE High to CE1 Low Setup Time for Write OE High to Address Setup Time for Write LB and UB Write Pulse Overlap Symbol Min. tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO 65 0 40 40 40 -5 -5 0 12 12 12 12 0 -5 0 30 Max. 1000 -- -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *7 *8 *1, *2 *3 *3 *3 *3 *4 *5 *6 Unit Notes Notes *1: Maximum value is applicable if CE1 is kept at Low without any address change. If the relaxation is needed by system operation, please contact local FUJITSU representative for the relaxation of 1s limitation. *2: Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or tBR). *3: Write pulse is defined from High to Low transition of CE1, WE, or LB / UB, whichever occurs last. *4: Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5: Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6: Write recovery is defined from Low to High transition of CE1, WE, or LB / UB, whichever occurs first. *7: If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns after CE1 is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *8: If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. 8 (AE1.0E) MB82DP04183C -65L PRELIMINARY AC CHARACTERISTICS (Continued) POWER DOWN PARAMETERS Value Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE1 High Hold Time following CE2 High after Power Down Exit [not in SLEEP mode] CE1 High Setup Time following CE2 High after Power Down Exit Symbol Min. tCSP tC2LP tCHH tCHHP tCHS 10 65 300 70 0 Max. -- -- -- -- -- ns ns s ns ns *1 *2 *1 Unit Note Notes *1: Applicable also to power-up. *2: Applicable when 8M and 16M Partial mode is programmed. OTHER TIMING PARAMETERS Value Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time Symbol Min. tCHOX tCHWX tC2LH tCHH tT 10 10 50 300 1 Max. -- -- -- -- 25 ns ns s s ns *2 *1 Unit Note Notes *1: Some data might be written into any address location if tCHWX(min) is not satisfied. *2: The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it may violate AC specification of some timing parameters. 9 (AE1.0E) MB82DP04183C -65L PRELIMINARY AC CHARACTERISTICS (Continued) AC TEST CONDITIONS Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Between VIL and VIH Test Setup Value VDD * 0.8 VDD * 0.2 VDD * 0.5 5 Unit V V V ns Note AC MEASUREMENT OUTPUT LOAD CIRCUIT VDD 0.1F VSS DEVICE UNDER TEST 50pF OUT 10 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS READ Timing #1 (Basic Timing) tRC ADDRESS tASC CE1 tOE OE tOHZ tBA LB / UB tBLZ DQ (Output) tOLZ tCLZ tBHZ tCE ADDRESS VALID tCHAH tCP tCHZ tASC See Note. VALID DATA OUTPUT tOH Note: This timing diagram assumes CE2=H and WE=H. READ Timing #2 (OE & Address Access) tRC ADDRESS ADDRESS VALID tAA CE1 Low tASO OE tOE tAx tRC ADDRESS VALID tAA tOHAH See Note. LB / UB tOLZ DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT tOH tOH tOHZ Notes:This timing diagram assumes CE2=H and WE=H. 11 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) READ Timing #3 (LB / UB Byte Access) tAX ADDRESS tAA CE1, OE Low tBA LB tBA UB tBLZ DQ1-8 (Output) DQ9-16 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH tBA tRC ADDRESS VALID See Note. tAx VALID DATA OUTPUT Note: This timing diagram assumes CE2=H and WE=H. READ Timing #4 (Page Address Access after CE1 Control Access) tRC ADDRESS (A21-A3) tRC ADDRESS (A2-A0) tASC CE1 OE LB / UB tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access) VALID DATA OUTPUT (Page Access) tOH tOH tOH tOH tCE ADDRESS VALID ADDRESS VALID tPRC ADDRESS VALID See Note. tPRC ADDRESS VALID tPRC ADDRESS VALID tPAA tPAA tPAA tCHAH tCHZ Notes:This timing diagram assumes CE2=H and WE=H. 12 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) READ Timing #5 (Random and Page Address Access) tRC ADDRESS (A21-A3) ADDRESS (A2-A0) CE1 ADDRESS VALID tRC ADDRESS VALID See Note. tRC ADDRESS VALID tAx tAX tPRC ADDRESS VALID tRC ADDRESS VALID tPRC ADDRESS VALID tAA Low tASO OE tBA LB / UB DQ (Output) tOLZ tBLZ tOH tOE tPAA tAA tPAA tOH tOH tOH VALID DATA OUTPUT (Normal Access) VALID DATA OUTPUT (Page Access) Notes *1: This timing diagram assumes CE2=H and WE=H. *2: Either or both LB and UB must be Low when both CE1 and OE are Low. 13 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) WRITE Timing #1 (Basic Timing) tWC ADDRESS tAS CE1 tAS WE tAS LB, UB tOHCL OE DQ (Input) VALID DATA INPUT tDS tDH tBW tWR tBHP tWP tWR tWHP tAS ADDRESS VALID tCW tWR tCP tAS tAS See Note. Notes:This timing diagram assumes CE2=H. WRITE Timing #2 (WE Control) tWC ADDRESS tOHAH CE1 Low tAS WE tWHP LB, UB tOES OE tOHZ DQ (Input) VALID DATA INPUT VALID DATA INPUT tDS tDH tDS tDH tWP tWR tAS tWP tWR ADDRESS VALID tWC ADDRESS VALID See Note. Note: This timing diagram assumes CE2=H. 14 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) WRITE Timing #3-1 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1 Low tAS WE tWR LB tBS UB tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input) VALID DATA INPUT tDS tDH tDH tBH tWR tWP tWHP tBH tBS tAS tWP ADDRESS VALID tWC ADDRESS VALID See Note. Note: This timing diagram assumes CE2=H and OE=H. WRITE Timing #3-2 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1 Low tWR WE tAS LB tBS UB tDS DQ1-8 (Input) DQ9-16 (Input) VALID DATA INPUT tDH tBH tAS tBW tBW tWHP tBS tBH tWR ADDRESS VALID tWC ADDRESS VALID See Note. VALID DATA INPUT tDS tDH Note: This timing diagram assumes CE2=H and OE=H. 15 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) WRITE Timing #3-3 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1 Low ADDRESS VALID tWC ADDRESS VALID See Note. WE tAS LB tBS UB tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input) tDH tBW tWR tWHP tBS tBH tBH tAS tBW tWR tDS tDH VALID DATA INPUT Note: This timing diagram assumes CE2=H and OE=H. WRITE Timing #3-4 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1 Low ADDRESS VALID tWC ADDRESS VALID See Note. WE tAS LB tBWO DQ1-8 (Input) tAS UB tDS DQ9-16 (Input) tDH tDS tDH tBW tWR tBHP tDS tDH tAS tBW tWR VALID DATA INPUT VALID DATA INPUT tBW tWR tBHP tAS tBWO tBW tDS tWR tDH VALID DATA INPUT VALID DATA INPUT Note: This timing diagram assumes CE2=H and OE=H. 16 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) READ / WRITE Timing #1-1 (CE1 Control) tWC ADDRESS tCHAH CE1 tCP WE tCP tAS WRITE ADDRESS tCW tWR tASC tRC READ ADDRESS tCE tCHAH See Note. UB, LB tOHCL OE tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tCLZ tOH Notes *1: This timing diagram assumes CE2=H. *2: Write address is valid from either CE1 or WE of last falling edge. READ / WRITE Timing #1-2 (CE1 / WE / OE Control) tWC ADDRESS tCHAH CE1 tCP tWP WE tCP tAS WRITE ADDRESS tWR tASC tRC READ ADDRESS tCE tCHAH See Note. UB, LB tOHCL OE tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tOLZ tOH tOE Notes *1: This timing diagram assumes CE2=H. *2: OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 17 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) READ / WRITE Timing #2 (OE, WE Control) tWC ADDRESS tOHAH CE1 Low tAS WE tOES tWP tWR WRITE ADDRESS tRC READ ADDRESS tAA tOHAH See Note. UB, LB tASO OE tOHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tWHOL tOLZ tOE tOHZ tOH Notes *1: This timing diagram assumes CE2=H. *2: CE1 can be tied to Low for WE and OE controlled operation. READ / WRITE Timing #3 (OE, WE, LB, UB Control) tWC ADDRESS WRITE ADDRESS tRC READ ADDRESS tAA CE1 Low tOHAH tOHAH See Note. WE tOES UB, LB tBHZ OE tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tWHOL tBLZ tASO tAS tBW tWR tBA tBHZ tOH Notes *1: This timing diagram assumes CE2=H. *2: CE1 can be tied to Low for WE and OE controlled operation. 18 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) POWER-UP Timing #1 See Note. CE1 tCHS tC2LH CE2 tCHH VDD 0V VDD min Note: The tC2LH specifies after VDD reaches specified minimum level. POWER-UP Timing #2 See Note. CE1 tCHH CE2 VDD 0V VDD min Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2. 19 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) POWER DOWN Entry and Exit Timing See Note. CE1 tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP) Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset. Standby Entry Timing after Read or Write See Note. CE1 tCHOX OE tCHWX WE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for Standby mode from CE1 Low to High transition. 20 (AE1.0E) MB82DP04183C -65L PRELIMINARY TIMING DIAGRAMS (Continued) POWER DOWN PROGRAM Timing See Note. tRC ADDRESS MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Key*2 tCP CE1 tCP tCP tCP tCP tCP*3 OE WE LB, UB*4 DQ*3 RDa Cycle #1 RDa Cycle #2 RDa Cycle #3 X Cycle #4 X Cycle #5 RDb Cycle #6 Notes *1: The all address inputs must be High from Cycle #1 to #5. *2: The address key must confirm the format specified in page 5. If not, the operation and data are not guaranteed. *3: After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation. *4: Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low. 21 (AE1.0E) MB82DP04183C -65L PRELIMINARY PAD LAYOUT Please contact local FUJITSU representative for pad layout and pad coordinate information. PAD DESCRIPTION Pin Name A21 to A0 CE1 CE2 WE OE UB LB DQ16-9 DQ8-1 VDD VSS TEST/OPEN Address Input Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Upper Byte Control (Low Active) Lower Byte Control (Low Active) Upper Byte Data Input/Output Lower Byte Data Input/Output Power Supply Ground Test/Open (This pad should be left open. Do not use.) Description 22 (AE1.0E) MB82DP04183C -65L PRELIMINARY PACKAGE FOR ENGINEERING SAMPLES Pin Assignment (TOP VIEW) A B C D E F G H J K L M 8 7 6 5 4 3 2 1 NC NC NC NC A11 A8 WE NC LB A15 A12 A19 CE2 NC UB A6 A3 A21 A13 A9 A20 NC A18 A5 A2 NC A14 A10 A16 NC NC VSS NC NC NC NC DQ16 DQ8 DQ15 DQ7 DQ14 DQ13 DQ6 DQ5 DQ4 VDD VDD NC DQ12 A17 A4 A1 DQ2 DQ10 DQ11 DQ3 VSS A0 OE NC DQ1 CE1 DQ9 NC NC NC NC NC NC NC A7 (BGA-71P-M03) Pin Description Pin Name A21 to A0 CE1 CE2 WE OE UB LB DQ16-9 DQ8-1 VDD VSS NC Address Input Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Upper Byte Control (Low Active) Lower Byte Control (Low Active) Upper Byte Data Input/Output Lower Byte Data Input/Output Power Supply Ground No Connection Description 23 (AE1.0E) MB82DP04183C -65L PRELIMINARY PACKAGE FOR ENGINEERING SAMPLES (Continued) Package Pin Capacitance Test conditions: TA = 25C, f = 1.0 MHz Symbol CIN1 CIN2 CIO Description Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Test Setup VIN = 0V VIN = 0V VIO = 0V Typ. -- -- -- Max. 5 5 8 Unit pF pF pF Package View 71-pin Plastic FBGA Package (BGA-71P-M03) Package Dimentions (Preliminary Drawing) 71-pin plastic FBGA (BGA-71P-M03) Dimensions in mm (inch) 24 (AE1.0E) MB82DP04183C -65L PRELIMINARY FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fmk.fujitsu.com/ F0408 2003- 2004 FUJITSU LIMITED Printed in Japan 25 (AE1.0E) |
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